MIPS-CPU - Year 2 Instruction Architecture Projects

MIPS-CPU - Year 2 Instruction Architecture Projects

school

Oct 2021 - Jan 2022


  • A full MIPS-compatible CPU implemented in Verilog, including the ALU, Register File, and BUS modules.
  • The CPU can implement the full 48 ISA instructions and store and read external RAM with an increasingly difficult test testbench, as well as a customer-oriented report.
  • Explore more on Github